The present invention relates to an interface circuit of an LSI (Large Scale Integrated Circuit) with external bus lines, wherein low I/O (Input/Output) noise and low power consumption are realized by coding/decoding I/O signal so as to reduce status alteration thereof.
A low-weight coding is proposed recently for reducing the I/O noise and the power consumption by way of changing high-level (logic `1`) bits' rate or level alteration rate of binary parallel signals exchanged through bus lines by adding a redundant bit.
In the case of CMOS type interface circuit, through current flows for charging/discharging bus lines when signal bit status alters from low level to high level or vice versa. Therefore, current consumption of the CMOS type interface circuit increases in proportion to frequency of the bit status alteration (or switching). Furthermore, so called the simultaneous switching noise is derived when the majority bits alter their status because of voltage fluctuation induced by parasitic inductance of power supply lines themselves, owing to peak current flowing from the power supply or flowing to the ground.
This simultaneous switching noise, which degrades operational margin of the LSI, can be reduced by coding the binary signal so as to reduce the level alteration rate thereof.
The above coding technique is realized in a concrete LSI for the first time by us and its effective results to improve LSI interface performance is reported to 1996 IEEE Symposium, (pp. 144-145, 1996 Symposium on VLSI Circuits Digest of Technical Papers). FIG. 3 is a circuit diagram illustrating an example of coding/decoding circuits for reducing the level alteration rate.
The example of FIG. 3 applied to 8-bits' signal has an encoder 1 provided on an LSI chip A for encoding an output 8-bits' signal, and a decoder 2 provided on another LSI chip B for decoding a signal received from the encoder 1. For transmitting the 8-bits' signal, the encoder 1 converts the 8-bits' signal into a 9-bits' signal adding a redundant bit, which is transferred through bus lines 9b of 9-bits' width. Signs .backslash.8 and .backslash.9 marked on signal lines of FIG. 3 represent parallel bus lines of 8 and 9-bits' width, respectively, while signs x8 or x9 marked on circuit symbols represent that there are eight or nine circuit elements each connected to each of the parallel bus lines of 8 or 9-bits' width, respectively.
The encoder 1 comprises a first XOR (eXclusive OR) gate unit XOR1, a majority discrimination circuit 11, a second XOR gate unit XOR2, and a register 12 for outputting the 9-bits' signal to bus lines 9b through an output buffer OB.
The encoder 1 operates as follows.
Input 8-bits' signal is added with an MSB (Most Significant Bit) of logic `0`, which makes input 9-bits' signal. The first XOR gate unit XOR1 compares the input 9-bits' signal to output 9-bits' signal to be supplied to the output buffer OB from the register 12 and generates XOR logic of each 9 bit of the input 9-bits' signal and corresponding each bit of the output 9-bits' signal for obtaining logic difference between corresponding bits of the two signals. For example, when logic of the two signals is "010101010" and "101010101", XOR logic of the two signals becomes "111111111", while it becomes "000000000" when the two signals have the same logic.
The majority discrimination circuit 11 discriminates whether bits of the input 9-bits' signal, that is, the signal to be output at next clock, of different logic compared to the output 9-bits' signal actually being output, are the majority or not, by comparing bit number of logic `1` to that of logic `0` of output of the first XOR gate unit XOR1. When different bits are found to be the majority, the majority discrimination circuit 11 output a discrimination signal of logic `1`, and logic of every bit of the input 9-bits' signal is inverted by the second XOR gate unit XOR2 which outputs XOR logic of each bit of the input 9-bits' signal and the discrimination signal. Output of the second XOR gate unit XOR2 is registered in the register 12 to be output at the next clock through the output buffer OB to the bus lines 9b.
Thus, the status alteration number of the output 9-bits' signal on the bus lines 9b is always maintained less than half of its bit width.
FIG. 4 is a circuit diagram illustrating an example reported in the above Symposium of the majority discrimination circuit 11.
In the majority discrimination circuit 11 of FIG. 4, logic (x0, x1, . . . ,) x8) of each bit X0 to X8 of output of the first XOR gate unit XOR1 is connected to each gate of a parallel connection of 9 nMOSFETs MN10 to MN18, while inverted logic (x0.sub.--, x1.sub.--, . . . , x8.sub.--) of each thereof is connected to each gate of another parallel connection of 9 nMOSFETs MN10.sub.-- to MN18.sub.--. The parallel connection of the 9 nMOSFETs MN10 to MN18 is connected between a constant current supply composed of an nMOSFET MNCS1 and a drain of a first pMOSFET MP11 of an operational amplifier and the other parallel connection of the nMOSFETs MN10.sub.-- to NM18.sub.-- is connected between the constant current supply and a drain of a second pMOSFET MP12 of the operational amplifier. Output terminal RES is connected to the drain of the second pMOSFET MP12.
Either of the first and the second pMOSFET MP11 and MP12 which is connected to the constant current supply through lower ON resistance of the two parallel connections becoming ON, the majority discrimination circuit 11 outputs the majority logic of the output of the first XOR gate unit XOR1.
The majority discrimination circuit 11 is the most complicated part of the coding/decoding circuit of FIG. 3 and takes the longest operational time.
Returning to FIG. 3, the decoder 2 of the LSI chip B, comprising a third XOR gate unit XOR3 checks the MSB of the received 9-bits' signal. When logic of the MSB is `0`, lower 8 bits are output as they are, and they are all inverted when logic of the MSB is `1`. Thus, the original 8-bits' signal is obtained. The above decoding can be performed by obtaining XOR logic of the MSB and each of the lower 8 bits of the received 9-bits' signal by the third XOR gate unit XOR3.
Although the coding/decoding circuits of FIG. 3 need one additional bus line for the redundant bit, they can reduce the simultaneous switching noise and the power dissipation into half at most by limiting the simultaneous alteration number within a half.
The coding/decoding circuits of FIG. 3 can reduce level alteration rate of signals transmitted through the bus lines 9b when the signals flow unidirectionally from the LSI chip A to the LSI chip B successively, coded by the encoder 1 by referring to outputting signals registered in the register 12. However, when the signals are transmitted bi-directionally on the same bus lines 9b, the above low-weight coding cannot reduce the signal level alteration at each transition of signal direction, transition between a signal from the LSI chip A to the LSI chip B and that from the LSI chip B to LSI chip A, for example, resulting in a simultaneous switching noise or a power dissipation at the transition. This is because the coding is performed without referring to receiving signals, as will be described referring to FIG. 5.
FIG. 5 is a circuit diagram illustrating an example wherein an LSI chip A and an LSI chip B, both simply provided with a coding and a decoding circuit, are connected through bus lines 9b.
In the bi-directional interface circuits of FIG. 5, there should be taken in consideration changes of signal direction that the LSI chip A transfers a signal to the LSI chip B just after receiving a signal from the LSI chip B, for example. When receiving signals from the LSI chip B in succession, the interface circuit of the LSI chip B can encode the signals on the bus lines 9b appropriately so that the level switching of the signals is maintained within half of the bit width. However, when a signal is transferred from the LSI chip A to the LSI chip B after signal succession from the LSI chip B, the encoder 1A of the LSI chip A cannot be informed of bit sequence on the bus lines 9b at preceding clock, being unable to generate a low-weight code having level alteration rate less than half. Therefor, there may occur, at worst, level alteration of all 9 bits, resulting in a still larger noise than that generated when the original 8-bits' signal is transferred without coding.